`timescale 1ns/1ns
`define DLY 0
module tb_divclk3;

reg	clk_in;
reg	rst_in;
wire	clk_out;

divclk3	u_divclk3(
	.clk_in(clk_in),
	.rst_in(rst_in),
	.clk_out(clk_out)
);

always #100 clk_in <= ~clk_in;

initial begin
	rst_in=1;
	clk_in=1;
	#200;
	rst_in=0;
	#200;
	rst_in=1;
end

initial begin
	$dumpfile("wave.dump");
	$dumpvars(0,tb_divclk3);
	#100000;
	$stop;
end

endmodule
